This application claims the priority of Korean Patent Application No. 10-2006-0009805, filed on Feb. 1, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to a data delay circuit and, more particularly, to a data delay circuit and a method that can adaptively reflect changes in an operating environment.
2. Discussion of Related Art
Generally, buffers or inverters are connected in a line or delay cells are used to delay data in a system. The delay periods of delay cells, however, are dramatically changed by factors such as a manufacturing process, an operating temperature or an operating voltage that cause the delay periods of delay cells in a minimum delay environment to more than double, as compared to the delay periods of the same delay cells in a maximum delay environment. Therefore, implementing a system using delay cells is not an appropriate way to obtain an expected delay signal.
FIG. 1 illustrates a circuit diagram of a conventional data delay circuit using a plurality of buffers BF.
Referring to FIG. 1, the conventional data delay circuit includes the buffers BFs and a plurality of capacitors CAPs. Because the conventional data delay circuit uses the simple buffers BFs and the capacitors CAPs, changes in an operating environment are directly reflected in the conventional data delay circuit. Therefore, the amount of change in the operating environment accumulates, and the minimum delay environment and the maximum delay environment produce different delay periods.
FIG. 2 illustrates a circuit diagram of a conventional data delay control apparatus. Specifically, FIG. 2 illustrates a conventional select delay circuit outputting a delayed data signal D_OUT in response to an input data signal D_IN.
Referring to FIG. 2, the conventional data delay control apparatus includes a plurality of delay paths DELAY1 through DELAYN and a selector MUX.
The operation of the selector MUX will now be briefly described. The selector MUX selects one of the delay paths DELAY1 through DELAYN according to some external factor and generates the delayed data signal D_OUT having various different delay periods in response to a select signal SEL. A processor (not shown) controls the selector MUX to select one of the delay paths DELAY1 through DELAYN in accordance with the select signal SEL. In this apparatus, however, the last delay path should be selected using the processor, and additional processing by the processor for obtaining necessary information is required for the processor to obtain accurate results. Therefore, without the additional processing by the processor, the conventional data delay control apparatus cannot effectively reflect the amount of change in the delay periods of the delay cells.